Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon) Review

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Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon) ReviewEveryone engaged in functional verification of digital hardware designs should read this book. It truly is comprehensive (which means that it can't go into depth on everything), but there is a very good amount of depth on most of the topics that should be covered by such a book, as much depth as 704 pages would allow.
This book is not about languages but about concepts, which are more important. Having said this, HDLs, HVLs and programming languages are used for illustration. Such concepts include re-use strategies for verification components (although the essential topic of revision control is sadly only mentioned in passing), formal verification and escape analysis.
I'm troubled by the very short Acknowledgments section. The authors were fortunate to have Scott Taylor as a reviewer. I worked with Scott on Compaq's Alpha microprocessor team and he is very talented. However, there are quite a few mistakes in the book and some paragraphs that could have been written more clearly. The authors would have benefited from more peer review. For example, Wolfgang Roesner and I were together at IBM on the POWER6 microprocessor in 2004 and 2005, but he never asked me for help!
At Cosmic Horizon, I had been working alone (until recently) on verification of the Sputnik microprocessor. For assistance in debugging the integer multiplication unit, I found it useful to create a cycle-accurate reference model. Working alone, I was forced to come up with many such ideas on my own, so I became curious about how other verification experts think. I bought the book to learn about that. Yes, I had worked at IBM myself, but I hadn't experienced everything while I was there, and I wanted to solidify in my mind why we did things the way we did. Since reading CFV, I have begun to morph Cosmic Horizon's FSS product according to some of the book's better ideas. For example, the test case database no longer contains expected results. Instead, I am developing a cycle-ignorant (my idea, necessary for architectural verification) reference model to generate expected results on-the-fly.
I was attracted to this language-nonspecific book written by three IBM microprocessor verification engineers because I focus on microprocessors (and would like to return to IBM), but the book successfully remains general enough to apply to non-microprocessor digital hardware designs as well. As I said, everyone should read this book.
And Wolfgang, call me next time!Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon) Overview

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Writing Testbenches: Functional Verification of HDL Models, Second Edition Review

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Writing Testbenches: Functional Verification of HDL Models, Second Edition ReviewThis book covers many facets of the task of creating testbenches. However, it doesn't seem to follow a very well thought out plan, and there are holes in the coverage.
Most of the book is a 'tips and tricks' coverage of how to get each language to do what it wasn't designed to do. He walks through various situations and says that something is easy to do in Specman (shows a short code fragment), but then goes into long detail in how to get around VHDL's limitations and get the same result. I realize these are probably pretty cool tricks, but not at all the approach for me (a beginner to writing sizable testbenches). If he kept up the coverage of all 4 languages throughout, it might be useful, but the focus shifts from language to language at whim. You won't learn how to write a testbench as much as you will learn some pitfalls to avoid.
One more gripe before I get to the parts I liked. Each chapter ends with a summary. The summary lists the author's favorite tricks, not a summary of the whole chapter. I found these to be not at all helpful in either deciding whether to read the chapter, or as a review of what was covered.
I did like the explanations of:
-- The importance of verification (now I know why I was hired)
-- Overview of all the lingo (I can sound like I know what I'm talking about now, even if I don't)
-- Merits of the various types of coverage (code/functional/transition ...)
-- Aspect Oriented Programming (e) and why it is useful (cool stuff!)
-- Using coverage to drive a random bench
That is only about 10% of the book, however. That 10% was really pretty good.
I see one of the other reviewers complained about lack of downloadable sourcecode. It is available at www.janick.bergeron.com/wtb along with an extensive errata list (I'd recommend taking the hour or so and marking up your book before reading).
I still give the book 3 stars, since it is the only verification book I've found, and I did really like parts of it. I read the book front to back, and would not particularly recommend this to others. Pick the parts that interest you, and skip the rest.Writing Testbenches: Functional Verification of HDL Models, Second Edition OverviewThe Second Edition of Writing Testbenches, Functional Verification of HDL Models presents the latest verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems.Topics included in the new Second Edition: *Discussions on OpenVera and e; *Approaches for writing constrainable random stimulus generators; *Strategies for making testbenches self-checking; *A clear blueprint of a verification process that aims for first time success; *Recent advances in functional verification such as coverage-driven verification process; *VHDL and Verilog language semantics; *The semantics are presented in new verification-oriented languages;*Techniques for applying stimulus and monitoring the response of a design; *Behavioral modeling using non-synthesizeable constructs and coding style; *Updated for Verilog 2001.

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Verification Methodology Manual for SystemVerilog Review

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Verification Methodology Manual for SystemVerilog ReviewI consider this book to be a good VMM Reference.
Please don't mistake this to be a complete SystemVerilog Bible. This is Verification Methodology Manual (VMM), and after reading this book, it's not a bad idea to think if this methodology is the right one for your project.
This book outlines several "rules", "recommendations", "suggestions" and "alternatives" in using VMM for your project. I found these to be useful to a certain extent. Although the examples weren't quite informative. For starters I would also suggest reading general book on object oriented programming along with this book.************* BUYING THIS BOOK? READ THIS: ***************
Before you buy this book, check if you/your office has Synopsys VCS installed (Along with Documentation). If you happen to have complete VCS installed, you would get this book (pdf version) for FREE along with the VCS documentation. I came to know about this after buying this book. Any ways, it is good to have a hard copy.
Also, I found it useful to have other SystemVerilog books along with this one. It makes life easy to understand a (new) language and (new) methodology.
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Verification Methodology Manual for SystemVerilog OverviewOffers usersthe first resource guide that combinesboth themethodology and basics of SystemVerilogAddresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly.Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.

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