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Network Processors : Architectures, Protocols and Platforms (Telecom Engineering) ReviewI read 'Network Processors' to learn more about this relatively new technology that is changing the way network security appliances are designed and deployed. Panos Lekkas' work seemed like the only book available that presented a broad, multi-vendor sweep of the network processor landscape. While the book has plenty of information to offer, I found it did not really live up to my expectations.Network processors are specialized computing chips built for high performance packet processing applications. I hoped 'Network Processors' would spend a good amount of time making the case for this technology, explaining why NPs are indispensable compared to general purpose CPUs. Unfortunately, I felt the book did not make a compelling case. Chapter 2, titled 'Network Processors: Justification,' is only 10 pages, with a single chart graphing bandwidth demand vs time. I would have liked to see head-to-head comparisons of NPs against CPUs for various network applications. The book spends a lot of time discussing technologies and concepts at the periphery of NPs; I think some of that space could have been put to better use.
Here is an example of why I felt let down by this book. In the preface, the author seems to assure the reader that he will answer questions others tend to ignore. On p. xix the author writes 'In numerous industry discussions, I have encountered experienced software engineers who have implemented cutting-edge protocols, but have no idea what concepts such as scheduling, backpressure, switching fabrics, and classification mean.' To be fair, the author does explain switching fabrics and classification. However, he says almost nothing about backpressure, and he certainly never explicitly defines it; the only mention is on p. 274.
Elsewhere, I thought the book was unnecessarily confusing. It's fine to cover deep technical details, but it helps to start with clear general definitions and progress to more difficult material. The following excerpt from p. 220, the second page of chapter 12, serves as part of the 'introduction' to content addressable memory: 'The principle of associative memory is based on the inverse mechanism of establishing a relationship between the input and a specific piece of information stored in the memory array.' This sentence is fine if the reader knows what 'associative memory' is, understands the 'inverse mechanism,' and can relate to 'the input' and a 'memory array.'
The layout of the book itself may have contributed to my difficulty with it. The font is one of the smallest I have ever encountered. The footnotes are so small as to be almost illegible. I like the hardcover binding, though.
Although not the author's fault, readers should be aware that many of the companies and some of the technologies in 'Network Processors' have disappeared. Each time I encountered a new company or product I checked to see if their Web page or product line still existed. For example, IBM's PowerNP receives an entire chapter; it was sold to Hifn in January 2004. In many cases, however, surviving vendors have not brought too many products to market since the book's late 2002 publication date.
I believe a second edition of 'Network Processors' would benefit from an editor who challenges the author to be more organized and generous with his audience. The book was built on a good idea -- bringing knowledge of NPs to general readers. A second edition should ensure that goal is met, since we do need to know more about this promising technology.Network Processors : Architectures, Protocols and Platforms (Telecom Engineering) OverviewNetwork processing units (NPUs) will be the occasion of sweeping changes in the network hardware industry over the next few years. This new breed of microchip impacts chip designers like Intel, equipment vendors like Cisco, application developers like IBM and Morotola, and an army of software engineers who spent the last decade working on protocols and network management solutions. A thoroughly practical dissection of the early NPU market, this designer's guide explains how network processors work and provides detailed information on all major commercial architectures, from features to design considerations. Comparative tables are a rich source of cross-industry info. Coverage includes traffic managers, classification chips, content-addressable memories, switch fabrics, security accelerators, storage coprocessors and NetASICs.
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