The Verilog® Hardware Description Language Review

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The Verilog® Hardware Description Language ReviewThis book should be used only by the experienced users that can filter out problematic sections.
Major problems:
- first chapter, "recommended" by authors for university courses, is extremely chaotic (begin..end blocks are called loops, exercises ask you to use loops before introducing them, etc.)
- cover of the latest edition claims coverage of the latest Verilog standard - unfortunately it is very poor coverage: new interesting features such as libraries and configurations are not mentioned at all!
- I had to work hard during many trainings to correct bad coding styles showing in students reading this book as their first Verilog publication
- the book is grossly overpriced...
Main advantage:
- good set of examplesThe Verilog® Hardware Description Language OverviewThis text presents the IEEE 1364-2001 standard of the Verilog language. The examples in this edition have been updated to illustrate the features of the language. A cross referenced guide to these features is provided, thus, designers already familiar with Verilog can quickly learn the features. Newcomers to the language can use it as a guide for reading "old" specifications. The book should prove to be a useful resource for engineers and students interested in describing, simulating and synthesizing digital systems. It is also ready for use in university courses, having been used for introductory logic design and simulation through advanced VLSI design courses. An appendix with tutorial help and a work-along style is keyed into the introduction for new students. Material supporting a computer-aided design course on the inner working of simulators is also included. "The Verilog TM Hardware Description Language" includes a CD containing Simucad's Silos TM 2001 Verilog Simulator, examples from the book and lecture slides. The simulator is limited in the size of descriptions it will simulate. A few of the language constructs are not recognized by this version of the simulator.

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Verilog® Quickstart: A Practical Guide to Simulation and Synthesis in Verilog (The Springer International Series in Engineering and Computer Science) Review

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Verilog® Quickstart: A Practical Guide to Simulation and Synthesis in Verilog (The Springer International Series in Engineering and Computer Science) ReviewAn excellent book for those who already understand programming and digital electronics. However, failure in some examples that could be more detailed.
I recommend to all who understand electronics and are programmers.
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Um excelente livro para quem já programa e entende de eletrônica digital. Porém, falha em alguns exemplos que poderiam ser mais detalhados.
Recomendo para todos os que entendem eletrônica e são programadores.Verilog® Quickstart: A Practical Guide to Simulation and Synthesis in Verilog (The Springer International Series in Engineering and Computer Science) OverviewFrom a review of the Second Edition 'If you are new to the field and want to know what "all this Verilog stuff is about," you've found the golden goose. The text here is straight forward, complete, and example rich -mega-multi-kudos to the author James Lee. Though not as detailed as the Verilog reference guides from Cadence, it likewise doesn't suffer from the excessive abstractness those make you wade through. This is a quick and easy read, and will serve as a desktop reference for as long as Verilog lives. Best testimonial: I'm buying my fourth and fifth copies tonight (I've loaned out/lost two of my others).' Zach Coombes, AMD

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Principles of Verifiable RTL Design Second Edition - A Functional Coding Style Supporting Verification Processes in Verilog Review

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Principles of Verifiable RTL Design Second Edition - A Functional Coding Style Supporting Verification Processes in Verilog ReviewIf you are looking for another book describing the Verilog Language Reference Manual then this book is not for you. If, however, to are looking for an excellent set of principles to build a design and verification philosophy then I highly recommend this book. The authors have produced an RTL centric view of design emphasizing the verification process. They argue that synthesis productivity gains have now placed the verification process in the critical path and that equal attention should be giving to coding for verification as is currently given to coding for synthesis. The chapter I particularly enjoyed, entitled "Bad Stuff," provides an excellent discussion with examples on coding styles that hinder efficient verification. The author's discussion of the problems with the use of X at the RT-level, due to X-state pessimism and optimism, and the need for 2-state RTL simulation is enlightening.Principles of Verifiable RTL Design Second Edition - A Functional Coding Style Supporting Verification Processes in Verilog OverviewThe first edition of Principles of Verifiable RTL Designoffered a common sense method for simplifying and unifying assertionspecification by creating a set of predefined specification modulesthat could be instantiated within the designer's RTL. Since therelease of the first edition, an entire industry-wide initiative forassertion specification has emerged based on ideas presented in thefirst edition. This initiative, known as the Open Verification LibraryInitiative (www.verificationlib.org), provides an assertion interfacestandard that enables the design engineer to capture many interestingproperties of the design and precludes the need to introduce new HDLconstructs (i.e., extensions to Verilog are not required).Furthermore, this standard enables the design engineer to `specifyonce,' then target the same RTL assertion specification over multipleverification processes, such as traditional simulation, semi-formaland formal verification tools. The Open Verification LibraryInitiative is an empowering technology that will benefit design andverification engineers while providing unity to the EDA community(e.g., providers of testbench generation tools, traditionalsimulators, commercial assertion checking support tools, symbolicsimulation, and semi-formal and formal verification tools). The second edition of Principles of Verifiable RTL Designexpands the discussion of assertion specification by including a newchapter entitled `Coverage, Events and Assertions'. All assertionsexampled are aligned with the Open Verification Library Initiativeproposed standard. Furthermore, the second edition provides expandeddiscussions on the following topics:
start-upverification;
the place for 4-state simulation;
raceconditions;
RTL-style-synthesizable RTL (unambiguous mapping togates);
more `bad stuff'.
The goal of the secondedition is to keep the topic current. Principles of Verifiable RTLDesign, A Functional Coding Style Supporting VerificationProcesses, Second Edition tells you how you can write Verilog todescribe chip designs at the RTL level in a manner that cooperateswith verification processes. This cooperation can return an order ofmagnitude improvement in performance and capacity from tools such assimulation and equivalence checkers. It reduces the labor costs ofcoverage and formal model checking by facilitating communicationbetween the design engineer and the verification engineer. It alsoorients the RTL style to provide more useful results from the overallverification process.

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