Principles of Verifiable RTL Design Second Edition - A Functional Coding Style Supporting Verification Processes in Verilog Review

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Principles of Verifiable RTL Design Second Edition - A Functional Coding Style Supporting Verification Processes in Verilog ReviewIf you are looking for another book describing the Verilog Language Reference Manual then this book is not for you. If, however, to are looking for an excellent set of principles to build a design and verification philosophy then I highly recommend this book. The authors have produced an RTL centric view of design emphasizing the verification process. They argue that synthesis productivity gains have now placed the verification process in the critical path and that equal attention should be giving to coding for verification as is currently given to coding for synthesis. The chapter I particularly enjoyed, entitled "Bad Stuff," provides an excellent discussion with examples on coding styles that hinder efficient verification. The author's discussion of the problems with the use of X at the RT-level, due to X-state pessimism and optimism, and the need for 2-state RTL simulation is enlightening.Principles of Verifiable RTL Design Second Edition - A Functional Coding Style Supporting Verification Processes in Verilog OverviewThe first edition of Principles of Verifiable RTL Designoffered a common sense method for simplifying and unifying assertionspecification by creating a set of predefined specification modulesthat could be instantiated within the designer's RTL. Since therelease of the first edition, an entire industry-wide initiative forassertion specification has emerged based on ideas presented in thefirst edition. This initiative, known as the Open Verification LibraryInitiative (www.verificationlib.org), provides an assertion interfacestandard that enables the design engineer to capture many interestingproperties of the design and precludes the need to introduce new HDLconstructs (i.e., extensions to Verilog are not required).Furthermore, this standard enables the design engineer to `specifyonce,' then target the same RTL assertion specification over multipleverification processes, such as traditional simulation, semi-formaland formal verification tools. The Open Verification LibraryInitiative is an empowering technology that will benefit design andverification engineers while providing unity to the EDA community(e.g., providers of testbench generation tools, traditionalsimulators, commercial assertion checking support tools, symbolicsimulation, and semi-formal and formal verification tools). The second edition of Principles of Verifiable RTL Designexpands the discussion of assertion specification by including a newchapter entitled `Coverage, Events and Assertions'. All assertionsexampled are aligned with the Open Verification Library Initiativeproposed standard. Furthermore, the second edition provides expandeddiscussions on the following topics:
start-upverification;
the place for 4-state simulation;
raceconditions;
RTL-style-synthesizable RTL (unambiguous mapping togates);
more `bad stuff'.
The goal of the secondedition is to keep the topic current. Principles of Verifiable RTLDesign, A Functional Coding Style Supporting VerificationProcesses, Second Edition tells you how you can write Verilog todescribe chip designs at the RTL level in a manner that cooperateswith verification processes. This cooperation can return an order ofmagnitude improvement in performance and capacity from tools such assimulation and equivalence checkers. It reduces the labor costs ofcoverage and formal model checking by facilitating communicationbetween the design engineer and the verification engineer. It alsoorients the RTL style to provide more useful results from the overallverification process.

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