Digital VLSI Design with Verilog: A Textbook from Silicon Valley Technical Institute Review

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Digital VLSI Design with Verilog: A Textbook from Silicon Valley Technical Institute ReviewVerilog is one of the key languages for chip layout. Not especially difficult, but you still have to somehow learn it. You can easily get manuals on Verilog, but those aren't well suited as a learning pedagogy. The attraction of this book is that it lays out [pun intended] just such a learning path. The chapters explain various aspects of the language. In toto, you get a pretty exposure to most of the language.
Plus, Verilog allows powerful simulations of chips. Necessary to reduce the cost of actually fabricating a functioning design. Another advantage of the book is that you learn how to use Verilog for design for testing, and for doing that testing.Digital VLSI Design with Verilog: A Textbook from Silicon Valley Technical Institute OverviewThis unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project.In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs.Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the accompanying CD-ROM. For a reader with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back-annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.Coverage of specific devices includes basic discussion and exercises on flip-flops, latches, combinational logic, muxes, counters, shift-registers, decoders, state machines, memories (including parityand ECC), FIFOs, and PLLs. Verilog specify blocks, with their path delays and timing checks, also are covered.

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