Verification Methodology Manual for SystemVerilog Review

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Verification Methodology Manual for SystemVerilog ReviewI consider this book to be a good VMM Reference.
Please don't mistake this to be a complete SystemVerilog Bible. This is Verification Methodology Manual (VMM), and after reading this book, it's not a bad idea to think if this methodology is the right one for your project.
This book outlines several "rules", "recommendations", "suggestions" and "alternatives" in using VMM for your project. I found these to be useful to a certain extent. Although the examples weren't quite informative. For starters I would also suggest reading general book on object oriented programming along with this book.************* BUYING THIS BOOK? READ THIS: ***************
Before you buy this book, check if you/your office has Synopsys VCS installed (Along with Documentation). If you happen to have complete VCS installed, you would get this book (pdf version) for FREE along with the VCS documentation. I came to know about this after buying this book. Any ways, it is good to have a hard copy.
Also, I found it useful to have other SystemVerilog books along with this one. It makes life easy to understand a (new) language and (new) methodology.
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Verification Methodology Manual for SystemVerilog OverviewOffers usersthe first resource guide that combinesboth themethodology and basics of SystemVerilogAddresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly.Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.

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