SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design and Modeling Review

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SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design and Modeling ReviewHere are my opinions after buying and reading the book.
- If you are student / fresher who wants to "learn" System Verilog then skip this book. This book assumes that you already know Verilog well.
- This book deals only with design. Authors plan to come up with one more for Verification.
- If you have plenty of cash ($130 for design and $130 for verification book) or your rich company pays for your books then go ahead and add this book to your library. If not then read free LRM http://www.eda.org/sv/SystemVerilog_3.1a.pdf
- Practice, practice, practice. Just by reading Verilog books no one has become a good design/verification engineer.
(...)Verilog won't become IEEE standard as it is. Thus this book will be superceded by a version which is slightly different anyway.SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design and Modeling OverviewSystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs.This book, SystemVerilog for Design, addresses the first aspect of the SystemVerilog extensions to Verilog. Important modeling features are presented, such as two-state data types, enumerated types, user-defined types, structures, unions, and interfaces. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. A companion to this book, SystemVerilog for Verification, covers the second aspect of SystemVerilog.

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